Intel EMIB-T breaks past existing AI and HPC scaling limits, enabling complex multi-die systems with 10x+ reticle dies and high-bandwidth HBM4e DRAM.

Intel's Embedded Multi-die Interconnect Bridge with Through-silicon Via technology (EMIB-T) represents a significant advancement in advanced packaging solutions for AI and HPC workloads. Demonstrated in full force at IEEE 2026 (ECTC), EMIB-T builds on Intel's existing EMIB technology—which has attracted customers including TeraFab, Google, and NVIDIA since entering mass production in 2017—by adding through-silicon via capabilities that substantially increase performance and scalability.

The fundamental goal of EMIB is to provide high-speed, cost-effective interconnectivity that bridges multiple chiplets together. EMIB has demonstrated substantial advantages over TSMC's CoWoS packaging solutions, enabling more flexible and larger compute architectures without the cost and power penalties of competing approaches. As a silicon bridge, EMIB is also considerably smaller than existing packaging techniques, reducing manufacturing risk.

EMIB-T combines the fine-pitch interconnect density of 2.5D integration with the vertical scaling benefits of through-silicon-via architectures. Recent scaling achievements include reducing the First Layer Interconnect (FLI) bump pitch to 25 micrometers and expanding package form factors to over 120 mm × 120 mm, enabling more than nine reticles of compute and memory silicon content on a single package. The technology supports reliable high-speed signaling exceeding 12 Gb/s for HBM4e memory, with demonstrated bandwidth densities of 265 GB/s/mm² achieved through 3D vertical integration of SRAM chiplets. At these densities, die-to-die connectivity accounts for less than 15% of total power consumption, with energy efficiency reaching as low as 0.15 pJ/bit at lower frequencies—enabling future hyper-large form factor packages up to 240 × 240 mm.

Unlike EMIB-M, which routes power around the silicon bridge through MIM capacitors, EMIB-T routes power directly through the bridge via TSVs, enabling greater scale-up density. Two distinct EMIB-T package configurations have been proposed, incorporating Application-Specific Integrated Circuits, HBM, and I/O dies with 448G SerDes data rates and optimized power delivery, thermal management, and redundancy solutions designed for yield. Beyond 10 reticle die areas have been successfully encapsulated, with void-free processes demonstrated across 2.5D and 3D packaging architectures. Intel's roadmap indicates future capabilities enabling complete systems-on-package to meet emerging HPC and AI demands.