NVIDIA positions Vera CPU as anchor compute platform for next-generation AI infrastructure, moving beyond GPU-only strategy.

Nvidia is expanding its dominance in AI infrastructure with the launch of its Vera CPU, a processor designed to handle the orchestration layer of emerging agentic AI systems. Unveiled at GTC 2026, the chip signals a fundamental shift in how AI infrastructure is being built—elevating the CPU from a supporting component to a central control plane for AI workloads. During the GTC keynote, Nvidia CEO Jensen Huang stated: "The CPU is no longer simply supporting the model; it's driving it." As AI moves from training to production, the bottleneck is shifting away from GPUs alone and toward orchestration, inference coordination, and real-time execution. Agentic AI systems—built to execute tasks, call tools, and manage multi-step workflows—require significant CPU resources to coordinate thousands of concurrent processes and maintain runtime environments.

Vera builds on Nvidia's Grace architecture but introduces a design optimized for high concurrency and sustained utilization. The processor features 88 custom, Arm-based "Olympus" cores, with each core able to run two tasks using Nvidia Spatial Multithreading, coupled with LPDDR5X memory delivering up to 1.2 TB/s of bandwidth and a second-generation Scalable Coherency Fabric for multi-tenant performance. According to Matt Kimball, vice president and analyst at Moor Insights & Strategy, "Traditional x86 wasn't designed for this. Vera was. It is effectively an AI CPU—built for agentic and reinforcement learning workloads." Kimball emphasized that architectural innovations including "Spatial Multithreading, neural branch prediction, a PyTorch-optimized instruction buffer, a graph database prefetch engine" change the performance profile in ways that more cores and memory alone do not.

Vera is tightly integrated into Nvidia's next-generation platform strategy. Within the Vera Rubin NVL72 platform, Vera CPUs are paired with GPUs via NVLink-C2C, delivering up to 1.8 TB/s of coherent bandwidth—approximately 7x the bandwidth of PCIe-based systems. Vera also serves as the host CPU for HGX Rubin NVL8 systems, acting as the control layer for GPU-dense AI clusters. Rack-scale Vera systems support more than 22,000 concurrent CPU environments and feature integrated networking and data processing via BlueField DPUs and ConnectX SuperNICs, reflecting a shift from batch processing to continuous execution and from single models to distributed, multi-agent systems.

Nvidia has secured broad support from collaborators and early adopters including Meta Platforms, Alibaba, ByteDance, Oracle Cloud Infrastructure, CoreWeave, Nebius Group, and Lambda, alongside OEMs including Dell Technologies, Hewlett Packard Enterprise, Lenovo, and Supermicro. Kimball highlighted Meta's adoption as particularly significant, noting: "Meta's adoption isn't a pilot. It shows they want to ensure those millions of GPUs are constantly fed." He also emphasized power efficiency as a defining factor: "It does all of this at lower power than x86. In a power-constrained data center world, that's not a feature—it's a fundamental shift."

Vera represents a structural shift in AI infrastructure beyond a conventional CPU launch. While GPUs and model scale have defined recent years, the move to production AI is exposing a new bottleneck: system orchestration. As agentic AI workloads scale, the challenge is coordinating thousands of processes in real time, re-centering the CPU as critical to AI performance. Nvidia's strategy reflects ambition to extend dominance beyond accelerators into the control plane of AI systems, positioning itself as a full-stack provider owning both execution and orchestration. This creates immediate advantages in Nvidia-centric environments while raising competitive pressure on traditional CPU vendors like Intel and AMD, which must now adapt general-purpose architectures to AI-native workloads. If agentic AI scales as expected, the data center will evolve into a coordinated system of real-time processes where competitive advantage shifts from individual chips to control of the entire system.