AMD's upcoming RDNA 5 and UDNA GPU architectures may ship in multiple configurations with 96, 40, 24, and 12 compute unit options.

Kepler_L2, a leaker with a track record of accuracy on AMD and Intel information, has posted block diagrams of at least four AMD RDNA 5 / UDNA SKUs to the Anandtech Forums. The top-tier die features 8 Shader Arrays with two shader engines each, totaling 16 shader engines, with 6 compute units per shader engine for a combined total of 96 Compute Units. Each Shader Engine has its own RB (Render Backend) unit connected to a central SoC block containing the Graphics Command Processor, Graphics Engine, HWS, and L2 cache. The die includes 16 Unified Memory controllers at 32-bit each, providing a maximum bus size of 512-bit, and could pack up to 128 MB of Infinity Cache if AMD maintains its current configuration.

The next variant in the stack features 40 Compute Units across 8 Shader Engines arranged in 4 Shader Arrays, with 5 CUs per Shader Engine. This configuration includes 6 memory controllers, yielding a 192-bit bus interface, and could support up to 48 MB of total Infinity Cache. The entry-level configurations scale from 24 down to 12 CUs: the 24 CU die contains four shader engines/arrays with 6 compute units per engine and 8 memory controllers (either 16-bit or 32-bit); the smallest die features just two shader arrays with 6 compute units total and 4 memory controllers (either 64-bit or 16-bit). These smaller variants might include 32 MB and 16 MB of Infinity Cache respectively.

Kepler also noted that one RDNA 5 Compute Unit is equivalent to a single RDNA 4 WGP (Work Group Processor), meaning the actual core count would be twice the reported CU count, since RDNA 4 WGPs contained two Compute Units each. Additionally, the Instinct lineup's CDNA 5 architecture is set to introduce increases in local cache, rising from 32KB L0 and 160 KB LDS cache on CDNA 4 to 448 KB of Shared L0/LDS cache in the MI400 series. While these are datacenter parts, the unified UDNA designation suggests these architectural improvements may extend to consumer-tier chips.

According to separate reporting from Chiphell forum member ZhangZhonghao, the RDNA 4 lineup may feature four configurations: a very large top-tier die, followed by mid-tier, small-tier, and tiny-tier SKUs. AMD's next-generation gaming lineup is expected to enter mass production by Q2 2026, coinciding with NVIDIA's "SUPER" series release and Intel's BMG-G31 "Big Battlemage" lineup launch. Both rumors should be treated with appropriate caution pending official AMD announcements.