NVIDIA is deploying its Vera CPU across chip design workflows, achieving up to 1.5x performance gains in critical EDA to

Modern chip design demands increasingly sophisticated tools, and the complexity of developing CPUs, GPUs and AI systems continues to grow. To address this challenge, NVIDIA is collaborating with industry leaders Cadence and Synopsys to optimize electronic design automation applications specifically for the NVIDIA Vera CPU. The company is now deploying Vera across EDA workflows used to develop its next generation of processors, demonstrating how high-performance CPU architecture can accelerate demanding engineering workloads.

What drives this investment is the pace of chip production itself. The speed of EDA simulation, verification and implementation directly influences the tempo at which the industry can develop new technologies, ultimately determining how quickly engineering teams can bring products to market. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations using logic simulation, formal verification and digital implementation technologies. While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance because they require fast individual cores, efficient memory systems and strong overall throughput.

NVIDIA's initial testing included applications from both partners. Cadence Jasper, a formal verification platform that uses smart proof technology and machine learning to find and fix bugs early in the design cycle, showed up to 1.5x higher performance on selected workloads. Synopsys VCS, a high-performance functional verification solution used to simulate and validate complex chip designs before fabrication, demonstrated similar results with the same number of cores. Beyond these benchmark results, NVIDIA is working closely with both companies on application profiling, software optimization and system-level tuning to improve engineering productivity across a broader range of workflows.

Vera combines eighty-eight custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric, delivering strong per-core performance, high memory bandwidth and consistent low latency. These capabilities are particularly important for workloads that mix latency-sensitive jobs with large-scale regression testing, as faster execution shortens individual verification runs while greater throughput enables engineers to evaluate more design alternatives within the same development window. Because verification and implementation stages are interconnected, improvements in verification throughput help organizations identify issues earlier and reduce costly downstream design iterations.

The deployment of Vera reflects a broader strategy of accelerating each workload with the compute architecture best suited to the task. In EDA, GPUs and AI continue to speed many algorithms, while high-performance CPUs remain essential for critical simulation, verification and implementation workloads. Looking ahead, NVIDIA plans to build on Vera with the next-generation Rosa CPU powered by the NVIDIA Rigel core while continuing to optimize leading EDA applications across its CPU roadmap. By using NVIDIA CPUs to design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering with each generation helping build the next.