AMD, Intel, and Nvidia unveiled datacenter and AI chip roadmaps, detailing next-gen architectures and timelines.

At Computex in Taipei this week, Intel, AMD, and Nvidia revealed their latest datacenter and AI offerings alongside a glimpse of their respective roadmaps extending into 2027. Nvidia CEO Jensen Huang announced the company's acceleration to a yearly GPU release cadence, naming its next-generation architecture Rubin and introducing an all-new Vera CPU coming in 2026. While these components often capture attention, it's important to recognize that Nvidia's highest-end accelerators aren't standalone PCIe cards but entire platforms—parts like the B100 and B200 ship in packs of eight as part of Nvidia's DGX or HGX platform, complete with the system and cluster networking required for deployment at scale.

Nvidia's 2025 roadmap introduces the Blackwell Ultra GPU and Spectrum Ultra Ethernet switches, with the Ultra GPU featuring eight stacks of 12-high HBM3e memory. The next architectural evolution arrives in 2026 with Rubin, which will use HBM4 memory, alongside the Vera CPU replacing the Grace architecture. Nvidia plans to deploy 1.6 Tbps InfiniBand and Ethernet switches with matching ConnectX-9 SuperNICs, while NVLink 6 switches will see bandwidth double from 1.8 TBps to 3.6 TBps. The roadmap extends into 2027 with a Rubin Ultra GPU featuring twelve stacks of HBM4 memory—a departure from the more aggressive timeline pitched to investors last year, which had faced considerable challenges, particularly regarding PCIe bandwidth availability in 2025.

AMD is pursuing an even more aggressive path, with CEO Lisa Su announcing a yearly GPU release cadence. The company's Instinct MI300-series accelerators, based on its CDNA 3 architecture, offer notable advantages over Nvidia's H100 and H200-series in floating-point performance, memory bandwidth, and capacity. AMD intends to extend this lead with the MI325X launching in Q4—a HBM3e-boosted version of the MI300X with 50 percent more capacity—followed by the CDNA 4 Instinct MI350 in 2025, which will feature 288 GB of HBM3e and move to a 3nm process node. The CDNA 4 architecture will add support for lower-precision 4-bit and 6-bit floating-point data types, bringing it into parity with Nvidia's Blackwell, with an additional "CDNA next" architecture planned for the following year bringing "significant architectural upgrades."

AMD also teased its 5th-generation Epyc CPU family, codenamed Turin, due later this year with up to 192 cores—twice that of its 4th-generation Genoa parts and 50 percent more than its cloud-optimized Bergamo SKUs. Meanwhile, Intel unveiled a 144 e-core datacenter CPU as the first of several Xeon 6 products planned for the coming quarters, with the Xeon 6 6700E processors offering 64 to 144 cores across two platforms: a smaller, lower-power 6700-series and a larger, 500W 6900-series configuration. Intel's Gaudi3 accelerator remains on track alongside this phased Xeon 6 rollout.