Intel provides product development updates on Rialto Bridge discrete GPU and Falcon Shores XPU acceleration programs.

Intel shared details of its high-performance computing chip roadmap Tuesday at the International Supercomputing Conference in Hamburg, Germany. The semiconductor giant has recently carved out a separate group of products for HPC applications, developing versions of Xeon Scalable CPUs starting with a high-bandwidth-memory variant of the forthcoming Sapphire Rapids chips. This chip will sport up to 64GB of HBM2e memory, giving it quick access to very large datasets. Intel's datacenter GPUs will start later this year with the much-hyped Ponte Vecchio chip that will compete against Nvidia's A100 and AMD's Instinct MI200 chips, featuring up to 128GB of HBM2e memory to tackle a mix of HPC and AI workloads. The Sapphire Rapids HBM variant and Ponte Vecchio will power the US Department of Energy's in-development exascale supercomputer expected to fire up later this year.

Succeeding Ponte Vecchio is Rialto Bridge, which will sport up to 160 cores of Intel's Xe GPU architecture. According to Jeff McVeigh, the head of Intel's Super Compute Group, this will help Rialto Bridge provide around 30 percent better performance than Ponte Vecchio for applications. To achieve the highest performance possible, Intel plans to provide a power-hungry, 800-watt module that will be liquid cooled and fit into the OAM 2.0 form factor used by hyperscalers like Facebook parent company Meta and Microsoft. Intel expects to start sampling Rialto Bridge in mid-2023 and is promising "software consistency" between Ponte Vecchio and Rialto Bridge to ease developer transition.

What comes after Rialto Bridge is even more significant: Intel is considering Falcon Shores a descendant of both Ponte Vecchio and Sapphire Rapids HBM because it will combine x86 CPU cores and Xe GPU cores in a single package, which Intel is calling an "XPU." Intel said Falcon Shores will provide 5x higher performance-per-watt, memory capacity, and memory bandwidth than "current platforms," and will have 5x greater compute density in an x86 socket than the best option available now, which is AMD's third-generation Epyc processor with 64 cores. The chip will be made using one of Intel's "Angstrom-era" manufacturing processes, likely Intel 20A or Intel 18A, and is targeted for a 2024 launch.

Falcon Shores will come in different configurations of x86 CPU cores and Xe cores, with some variants containing only x86 cores while others contain only Xe cores. This flexible design allows Intel to create chips that can serve as a CPU, a GPU, or a combination of the two that will share memory at what Intel said will be an "extreme bandwidth." To ease developer adoption, Intel is promising a "simplified programming model" that will allow developers to decide how to map different parts of an application to the chip's x86 and Xe cores. The hybrid design is made possible by using tiles, also known as chiplets, which will give Intel greater flexibility in how chips are configured much later in the design process. McVeigh called this use of tiles to enable more flexible design choices a "revolutionary" change in the way chips are created, stating that "if new trends come along, we can more easily adapt and place those within the design."